A 2.6-mW 4-b 4.8-GS/s Dual-Edges-Triggered Time-Based Flash ADC

This paper proposes a 4-b 5-GS/s time-based flash ADC in 45-nm digital CMOS technology, which utilizes both rising and falling edges of the clock for sampling and quantiza-tion. A dual-edge-triggered scheme reduces the dynamic power consumption of a voltage-to-time converter and the clock buffers by half. We doubled both the reset and the available regeneration times by interleaving the time comparators. The ADC has a low input capacitance and the calibration circuit is included on-chip for suppressing various mismatches. The prototype running at 5 GS/s consumes 2.6 mW from a 0.8-V supply and achieves a signal-to-noise and distortion ratio of 26.19 dB at Nyquist.